AU-KBC RESEARCH CENTRE
The semiconductor industry has been growing at an exponential pace (Moore's law) over the past few decades and has been the driving force behind rapid strides made by many industries such as mobile devices, telecommunication equipment manufacturers, information technology systems, office automation, industrial machinery, automobiles and several other industries. However, industry experts feel the country has been facing a serious shortage in VLSI design professionals and researchers. The real solution to solving this issue is for engineering institutions to offer good quality VLSI education heavily backed with hands-on training sessions conducted by experts with proven track record in the industry.
We, a group of alumni identified below, are former students of Prof. C.N.Krishnan and Prof. P.V.Ramakrishna, and are presently holding leading positions in reputed microprocessor and chip-design organizations. We have now come together in an effort to impart our learnings in VLSI design from the last two decades to the student community. We believe that the overall know-how of the student community will improve, as the effort, tries to bridge the gaps between the Academia and the Industry.
We are glad that the AU-KBC Research Centre , itself a creation of an alumnus of the MIT Campus of the university, has agreed to host this program and provide all support to it.
The mode and quantum of deliveries is being currently worked upon, however, the big picture is, we plan to start off with a bunch of lectures followed by an experimental tape-out plan. This is purely a voluntary effort, without any expectations by the Alumni, whose only intention is to make the Alma-mater proud!
Brief outline for the program:
Initially, attempt an array of organized lectures delivered by the Alumni group on various topics (listed below) over the next several weeks and
Follow up the above with a fully student driven experimental tape out (semiconductor chip design and test) mentored by highly experienced Alumni.
Who Gets to Attend:
Preferably, must be in the final year B.E / B.Tech programs in Electronics and Communication. This being an interdisciplinary field, interested final year B.E students from Electrical, Electronics & Instrumentation, Computer Science and Engineering streams also will also be considered .
Duration of the program:
This is an exploratory exercise: the current plan is to start with the first module of lectures in Jan 2019. The subsequent modules and the Tapeout plan will be published later. Subsequently, the following are the probable list of other
|No.||Date(2019)||Course work / Training||Duration|
|1||5th Jan||ASIC Design Methodology||8 hrs|
|2||12th Jan||IP SOC Design and Integration||4 hrs|
|3||19th Jan||IO Design/Interface issues||4 hrs|
|4||26th Jan||Verification - An Industry Survey||4 hrs|
|5||2nd Feb||RTL to GDS - Tapeout Process||8 hrs|
Subsequently, the following are the probable list of other lectures that may be offered. The offering will depend on the success of initial set of steps and the timeframe would be decided by the Alumni team.
|No.||Course work / Training||No.||Course work / Training|
|1||Compute Arch and RISC-V fundamentals||11||GDS Building and Physical Verification|
|2||Analog Circuit Design||12||Tape Sign Off Checks|
|3||Mixed Signal Integ||13||Post-Silicon Validation|
|4||Floor plan Intro||14||Testvector Generation|
|5||Synthesis Intro||15||Power & Signal Integrity|
|6||DFT & BIST Intro||16||Timing Convergence : STA|
|7||Board Design Issues||17||Place & Route Tecniques|
|8||SystemvVerilog and UVM with labs||18||Reliability - Electrical stress, Ageing, EM, ESD|
|9||Layout, matching, substrate noise||19||Program management Checklists|
|10||Elect, thermal and mech design||20||Analog mixed-signal test, DFT & BIST|
Experimental Tape-out Plan:
Our mission is to create a sustainable capability at Anna University to be able to tape student designs on a regular basis. We think students subscribing to this, stand to get immensely benefited in learning a process that is widely used in the industry. The possible tape out details are being currently evaluated, and the mission blueprint will be published by end of Q1-2019. To begin with, the short term (6month time period) goal is to pick an open source design (like RISC cores etc.), tailor it to a specific application, and take it through the complete ASIC design flow to generate a manufacturable Silicon.
List of Alumni:
The following is an initial list of Alumni who has expressed interest in contributing. This list will grow as time progresses.
|Alumni Name||Expe-rience||Companies worked for||Expertise|
|Adalarasu Mahadevan||22 Yrs||Cadence Design, Qualcomm||RTL 2 GDS|
|Lakshmanan Balasubramanian||21 Yrs||Texas Instruments||Analog Circuit|
|Vijayabhaskar Sankaranarayanan||20 Yrs||Hewlett Packard, Cypress Semi,Qualcom||SOC Integration, Verification, Physical Design|
|Ramkumar Radhakrishnan||20 Yrs||Cisco Systems||Verification|
|Sundar Govindarajan||19 Yrs||Multicoreware Systems||Processor Design|
|DesinghDevibalan||19 Yrs||Philips, NXP||Embedded Systems|
|Baburaj||15 Yrs||Microchip, Ambit Wireless||uP/uC Design|
|Sudarshan J||15 Yrs||Aura Semi||Analog Design|
|Arun Chandrashekar||22 Yrs||Intel||Packaging|
To know more about this program , interested candidates have to attend the "Orientation Seminar" , 10.00 AM to 3.00PM, Saturday 15th Dec. 2018 at the AU-KBC Centre Lecture Hall, MIT Campus.
Register for this Seminar before 14th Dec. 2018 by writing to email@example.com, with copy to firstname.lastname@example.org and email@example.com